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| this is information on a product in full production. april 2012 doc id 16610 rev 2 1/51 51 l6566bh multimode controller for smps datasheet ? production data features selectable multimode operation: fixed frequency or quasi-resonant on-board 840 v high voltage startup advanced light load management low quiescent current (< 3 ma) adaptive uvlo line feedforward for constant power capability vs. mains voltage pulse-by-pulse ocp, shutdown on overload (latched or auto-restart) transformer saturation detection programmable frequency modulation for emi reduction latched or auto-restart ovp brownout protection -600/+800 ma totem pole gate driver with active pull-down during uvlo SO16N package applications industrial smps smps running off rectified 3-phase input line SO16N figure 1. block diagram + - + - z ero current detector 50 mv 100 mv v cc 915 7 zcd comp vff cs gd 4 11 3 line voltage feedforward 1.5 v + - + - 4.5v dis 8 latch leb 14v ref er e nc e voltages 5 v cc 10 internal supply vr ef uv lo voltage regulator & adaptive u vl o fmod 6 ic_latch disable uvlo q 12 + - + - 0.450v 0.485v ac_ok 16 13 ac_ fail uvlo_shf v cc 5.7v 1 hv soft-start & fault mngt 14 ss osc mod e/sc +- oscillator r s q mode selection & turn-on logic overvoltage protection 15 a 7.7v ocp pwm time out time out + - vth burst-mode low clamp & disable off2 off2 i hv hiccup-mode ocp logic 3 v 400 ua driver ocp2 + - 6.4v v cc i charge ovpl ovp ovpl ovp www.st.com
contents l6566bh 2/51 doc id 16610 rev 2 contents 1 description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 pin settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.1 connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3 electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.1 maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3.2 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 5.1 high voltage startup generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5.2 zero-current detection and triggering block; oscillator block . . . . . . . . . . 19 5.3 burst-mode operation at no load or very light load . . . . . . . . . . . . . . . . . . 22 5.4 adaptive uvlo . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.5 pwm control block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 5.6 pwm comparator, pwm latch and voltage feedforward blocks . . . . . . . . 25 5.7 hiccup-mode ocp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.8 frequency modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 5.9 latched disable function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 5.10 soft-start and delayed latched shutdown upon overcurrent . . . . . . . . . . . 32 5.11 ovp block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 5.12 brownout protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 5.13 slope compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.14 summary of l6566bh power management functions . . . . . . . . . . . . . . . 39 6 application examples and ideas . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 l6566bh contents doc id 16610 rev 2 3/51 7 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 8 order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 9 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 list of tables l6566bh 4/51 doc id 16610 rev 2 list of tables table 1. pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 table 2. absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 3. thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 table 4. electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 5. l6566bh light load management features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 6. l6566bh protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 table 7. external circuits that determine ic behavior upon ovp and ocp . . . . . . . . . . . . . . . . . . . 44 table 8. SO16N mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 table 9. order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 10. document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 l6566bh list of figures doc id 16610 rev 2 5/51 list of figures figure 1. block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2. typical system block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 figure 3. pin connection (through top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 figure 4. multimode operation with qr option active . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 5. high voltage startup generator: internal schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 figure 6. timing diagram: normal power-up and power-down sequences . . . . . . . . . . . . . . . . . . . . 18 figure 7. timing diagram showing short-circuit behavior (ss pin clamped at 5 v) . . . . . . . . . . . . . . 19 figure 8. v hv rating vs. temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 9. drain ringing cycle skipping as the load is gradually reduced . . . . . . . . . . . . . . . . . . . . . . 20 figure 10. operation of zcd, triggering and oscillator blocks (qr option active) . . . . . . . . . . . . . . . . 22 figure 11. load-dependent operating modes: timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 figure 12. addition of an offset to the current sense lowers the burst-mode operation threshold . . . . 23 figure 13. adaptive uvlo block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 14. possible feedback configurations that can be used with the l6566bh . . . . . . . . . . . . . . . 24 figure 15. externally controlled burst-mode operation by driving the comp pin: timing diagram. . . . 25 figure 16. typical power capability change vs. input voltage in qr flyback converters . . . . . . . . . . . 26 figure 17. left: overcurrent setpoint vs. vff voltage; right: line feedforward function block. . . . . . . . 27 figure 18. hiccup-mode ocp: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 9 figure 19. frequency modulation circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 figure 20. operation after latched disable activation: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . 32 figure 21. soft-start pin operation under different operating conditions and settings . . . . . . . . . . . . . 33 figure 22. ovp function: internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 23. ovp function: timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 figure 24. maximum allowed duty cycle vs. switching frequency for correct ovp detection. . . . . . . . 36 figure 25. brownout protection: internal block diagram and timing diagram . . . . . . . . . . . . . . . . . . . . 37 figure 26. voltage sensing techniques to implement brownout protection with the l6566bh . . . . . . 38 figure 27. slope compensation waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 28. typical low-cost application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 29. typical full-feature application schematic (qr operation) . . . . . . . . . . . . . . . . . . . . . . . . . 43 figure 30. typical full-feature application schematic (ff operation) . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 31. frequency foldback at light load (ff operation) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 32. latched shutdown upon mains overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 33. SO16N package drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 34. recommended footprint (dimensions are in mm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 description l6566bh 6/51 doc id 16610 rev 2 1 description the l6566bh is an extremely versatile current-mode primary controller ic, specifically designed for high-performance offline flyback converters running off rectified 3-phase input lines. it is also suited to single-stage, single-switch, input-current-shaping converters (single-stage pfc) for applications that must comply with en61000-3-2 or jeita-miti regulations. both fixed-frequency (ff) and quasi-resonant (qr) operation are supported. the user can choose either of the two depending on application needs. the device features an externally programmable oscillator: it defines the converter switching frequency in ff mode and the maximum allowed switching frequency in qr mode. when ff operation is selected, the ics work as a standard current-mode controller with a maximum duty cycle limited to 70% min. the oscillator frequency can be modulated to mitigate emi emissions. qr operation, when selected, occurs at heavy load and is achieved through a transformer demagnetization sensing input that triggers mosfet turn-on. under some conditions, zvs (zero-voltage switching) can be achieved. the converter?s power capability rise with the mains voltage is compensated by line voltage feedforward. at medium and light load, as the qr operating frequency equals the oscillator frequency, a function (valley skipping) is activated to prevent further frequency rise and keep the operation as close to zvs as possible. with either ff or qr operation, at very light load the ics enter a controlled burst-mode operation that, along with the built-in, non-dissipative, high-voltage startup circuit and the low quiescent current, helps keep the consumption from the mains low and meet energy saving recommendations. an innovative adaptive uvlo helps minimize the issues related to the fluctuations of the self-supply voltage due to transformer parasites. the protection functions included in this device are: not-latched input undervoltage (brownout), output ovp (auto-restart or latch-mode selectable), a first-level ocp with delayed shutdown to protect the system during overload or short-circuit conditions (auto- restart or latch-mode selectable), and a second-level ocp that is invoked when the transformer saturates or there is a short-circuit of the secondary diode. a latched disable input allows easy implementation of otp with an external ntc, while an internal shutdown prevents ic overheating. programmable soft-start, leading-edge blanking on the current sense input for greater noise immunity, slope compensation (in ff mode only), and a shutdown function for externally controlled burst-mode operation or remote on/off control complete the features of this device. l6566bh description doc id 16610 rev 2 7/51 figure 2. typical system block diagram v o u tdc l6566bh flyback dc-dc converter rectified & filtered m a in s volt a ge pin settings l6566bh 8/51 doc id 16610 rev 2 2 pin settings 2.1 connections figure 3. pin connection (through top view) 2.2 pin description n. c. gnd gd vcc fmod dis vff ss osc mode/ sc comp f e r v s c k o _ c a s v h zcd 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 am11479v1 table 1. pin functions n pin function 1hvs high voltage startup. the pin, able to withstand 840 v, is to be tied directly to the rectified mains voltage. a 1 ma internal current source charges the capacitor connected between the vcc pin (5) and gnd pin (3) until the voltage on the vcc pin reaches the turn-on threshold, it is then shut down. normally, the generator is re- enabled when the vcc voltage falls below 5 v to ensure a low power throughput during short-circuit. otherwise, when a latched protection is tripped the generator is re-enabled 0.5 v below the turn-on threshold, to keep the latch supplied; or, when the ic is turned off by the comp pin (9) pulled low, the generator is active just below the uvlo threshold to allow a faster restart. 2n.c. not internally connected. provision for clearance on the pcb to meet safety requirements. 3gnd ground. current return for both the signal part of the ic and the gate drive. all of the ground connections of the bias components should be tied to a track going to this pin and kept separate from any pulsed current return. 4gd gate driver output. the totem pole output stage is able to drive power mosfets and igbts with a peak current capability of 800 ma source/sink. l6566bh pin settings doc id 16610 rev 2 9/51 5vcc supply voltage of both the signal part of the ic and the gate driver. the internal high voltage generator charges an electrolytic capacitor connected between this pin and gnd (pin 3) as long as the voltage on the pin is below the turn-on threshold of the ic, after that it is disabled and the chip is turned on. the ic is disabled as the voltage on the pin falls below the uvlo threshold. this threshold is reduced at light load to counteract the natural reduction of the self-supply voltage. sometimes a small bypass capacitor (0.1 f typ.) to gnd might be useful to obtain a clean bias voltage for the signal part of the ic. 6fmod frequency modulation input. when ff mode operation is selected, a capacitor connected from this pin to gnd (pin 3) is alternately charged and discharged by internal current sources. as a result, the voltage on the pin is a symmetrical triangular waveform with the frequency related to the capacitance value. by connecting a resistor from this pin to pin 13 (osc) it is possible to modulate the current sourced by the osc pin and then the oscillator frequency. this modulation is to reduce the peak value of emi emissions by means of a spread-spectrum action. if the function is not used, the pin is left open. 7cs input to the pwm comparator. the current flowing in the mosfet is sensed through a resistor, the resulting voltage is applied to this pin and compared with an internal reference to determine mosfet turn-off. the pin is equipped with 150 ns min. blanking time after the gate-drive output goes high for improved noise immunity. a second comparison level located at 1.5 v latches the device off and reduces its consumption in the case of transformer saturation or secondary diode short-circuit. the information is latched until the voltage on the vcc pin (5) goes below the uvlo threshold, therefore resulting in intermittent operation. a logic circuit improves sensitivity to temporary disturbances. 8dis ic latched disable input. internally, the pin connects a comparator that, when the voltage on the pin exceeds 4.5 v, latches off the ic and brings its consumption to a lower value. the latch is cleared as the voltage on the vcc pin (5) goes below the uvlo threshold, but the hv generator keeps the vcc voltage high (see pin 1 description). it is then necessary to recycle the input power to restart the ic. for a quick restart, pull pin 16 (ac_ok) below the disable threshold (see pin 16 description). bypass the pin with a capacitor to gnd (pin 3) to reduce noise pick- up. ground the pin if the function is not used. 9comp control input for loop regulation. the pin is driven by the phototransistor (emitter- grounded) of an optocoupler to modulate its voltage by modulating the current sunk. a capacitor placed between the pin and gnd (3), as close to the ic as possible to reduce noise pick-up, sets a pole in the output-to-control transfer function. the dynamics of the pin are in the 2.5 to 5 v range. a voltage below an internally defined threshold activates burst-mode operation. the voltage at the pin is bottom-clamped at about 2 v. if the clamp is externally overridden and the voltage is pulled below 1.4 v, the ic shuts down. 10 vref an internal generator furnishes an accurate voltage reference (5 v 2%) that can be used to supply few ma to an external circuit. a small film capacitor (0.1 f typ.), connected between this pin and gnd (3), is recommended to ensure the stability of the generator and to prevent noise from affecting the reference. this reference is internally monitored by a separate auxiliary reference and any failure or drift causes the ic to latch off. table 1. pin functions (continued) n pin function pin settings l6566bh 10/51 doc id 16610 rev 2 11 zcd transformer demagnetization sensing input for quasi-resonant operation and ovp input. the pin is externally connected to the transformer?s auxiliary winding through a resistor divider. a negative-going edge triggers mosfet turn-on if qr mode is selected. a voltage exceeding 5 v shuts the ic down and brings its consumption to a lower value (ovp). latch off or auto-restart mode is selectable externally. this function is strobed and digitally filtered to increase noise immunity. 12 mode/sc operating mode selection. if the pin is connected to the vref pin (7), quasi- resonant operation is selected, the oscillator (pin 13, osc) determines the maximum allowed operating frequency. fixed-frequency operation is selected if the pin is not tied to vref, in which case the oscillator determines the actual operating frequency, the maximum allowed duty cycle is set at 70% min. and the pin delivers a voltage ramp synchronized to the oscillator when the gate-drive output is high; the voltage delivered is zero while the gate-drive output is low. the pin is to be connected to pin cs (7) via a resistor for slope compensation. 13 osc oscillator pin. the pin is an accurate 1 v voltage source, and a resistor connected from the pin to gnd (pin 3) defines a current. this current is internally used to set the oscillator frequency that defines the maximum allowed switching frequency of the l6566bh, if working in qr mode, or the operating switching frequency if working in ff mode. 14 ss soft-start current source. at startup, a capacitor css between this pin and gnd (pin 3) is charged with an internal current generator. during the ramp, the internal reference clamp on the current sense pin (7, cs) rises linearly starting from zero to its final value, therefore causing the duty cycle to increase progressively starting from zero as well. during soft-start the adaptive uvlo function and all functions monitoring the comp pin are disabled. the soft-start capacitor is discharged whenever the supply voltage of the ic falls below the uvlo threshold. the same capacitor is used to delay ic shutdown (latch off or auto-restart mode selectable) after detecting an overload condition (olp). 15 vff line voltage feedforward input. the information on the converter?s input voltage is fed into the pin through a resistor divider and is used to change the setpoint of the pulse-by-pulse current limitation (the higher the voltage, the lower the setpoint). the linear dynamics of the pin ranges from 0 to 3 v. a voltage higher than 3 v makes the ic stop switching. if feedforward is not desired, tie the pin to gnd (pin 3) directly if a latch-mode ovp is not required (see pin 11, zcd) or through a 10 k ? min. resistor if a latch-mode ovp is required. bypass the pin with a capacitor to gnd (pin 3) to reduce noise pick-up. 16 ac_ok brownout protection input. a voltage below 0.45 v shuts down (not latched) the ic, lowers its consumption and clears the latch set by latched protection (dis > 4.5 v, ss > 6.4 v, vff > 6.4 v). ic operation is re-enabled as the voltage exceeds 0.45 v. the comparator is provided with current hysteresis: an internal 15 a current generator is on as long as the voltage on the pin is below 0.45 v and is off if this value is exceeded. bypass the pin with a capacitor to gnd (pin 3) to reduce noise pick-up. tie to vcc with a 220 to 680 kw resistor if the function is not used. table 1. pin functions (continued) n pin function l6566bh electrical data doc id 16610 rev 2 11/51 3 electrical data 3.1 maximum rating 3.2 thermal data table 2. absolute maximum ratings symbol pin parameter value unit v hvs 1 voltage range (referred to ground) @ 25 c -0.3 to 840 v i hvs 1 output current self-limited v cc 5 ic supply voltage (icc = 20 ma) self-limited v fmod 6 voltage range -0.3 to 2 v v max 7, 8, 10, 14 analog inputs and outputs -0.3 to 7 v v max 9, 15, 16 maximum pin voltage (ipin 1 ma) self-limited i zcd 11 zero-current detector max. current 5 ma v mode/sc 12 voltage range -0.3 to 5.3 v v osc 13 voltage range -0.3 to 3.3 v p tot power dissipation @ t a = 50 c 0.75 w t stg storage temperature -55 to 150 c t j junction operating temperature range -40 to 150 c table 3. thermal data symbol parameter value unit r thja thermal resistance junction to ambient 120 c/w electrical characteristics l6566bh 12/51 doc id 16610 rev 2 4 electrical characteristics (t j = -25 to 125 c, v cc = 12, c o = 1 nf; mode/sc = v ref , r t = 20 k ? from osc to gnd, unless otherwise specified.) table 4. electrical characteristics symbol parameter test condition min. typ. max. unit supply voltage vcc operating range after turn-on v comp > v compl 10.6 23 v v comp = v compo 823 vcc on turn-on threshold (1) 13 14 15 v vcc off turn-off threshold (1) v comp > v compl 9.4 10 10.6 v (1) v comp = v compo 7.2 7.6 8.0 hys hysteresis v comp > v compl 4v v z zener voltage icc = 20 ma, ic disabled 23 25 27 v supply current i start-up startup current before turn-on, vcc = 13 v 200 250 a i q quiescent current after turn-on, v zcd = v cs = 1 v 2.6 2.8 ma icc operating supply current mode/sc open 4 4.6 ma i qdis quiescent current ic disabled (2) 330 2500 a ic latched off 440 500 high voltage startup generator v hv breakdown voltage (3) i hv < 100 a @ 25 c 840 v v hvstart start voltage i vcc < 100 a 65 80 100 v i charge vcc charge current v hv > v hvstart , vcc > 3 v 0.55 0.85 1 ma i hv, on on-state current v hv > v hvstart , vcc > 3 v 1.6 ma v hv > v hvstart , vcc = 0 0.8 i hv, off off-state leakage current v hv = 400 v 40 a v ccrestart vcc restart voltage vcc falling 4.4 5 5.6 v (1) ic latched off 12.5 13.5 14.5 (1) disabled by v comp < v compoff 9.4 10 10.6 reference voltage v ref output voltage (1) t j = 25 c; i ref = 1 ma 4.95 5 5.05 v v ref to t a l va r i a t i o n i ref = 1 to 5 ma, vcc = 10.6 to 23 v 4.9 5.1 v i ref short-circuit current v ref = 0 10 30 ma l6566bh electrical characteristics doc id 16610 rev 2 13/51 sink capability in uvlo vcc = 6 v; isink = 0.5 ma 0.2 0.5 v v ov overvoltage threshold 5.3 5.7 v internal oscillator f sw oscillation frequency operating range 10 300 khz t j = 25 c, v zcd = 0, mode/sc = open 95 100 105 vcc =12 to 23 v, v zcd = 0, mode/sc = open 93 100 107 v osc voltage reference (4) 0.9711.03v d max maximum duty cycle mode/sc = open, v comp = 5 v 70 75 % brownout protection vth threshold voltage voltage falling (turn-off) 0.432 0.450 0.468 v voltage rising (turn-on) 0.452 0.485 0.518 v i hys current hysteresis vcc > 5 v, v vff = 0.3 v 121518a v ac_ok_cl clamp level (1) i ac_ok = 100 a 3 3.15 3.3 v line voltage feedforward i vff input bias current v vff = 0 to 3 v, v zcd < v zcdth -1 a v zcd > v zcdth -0.7 -1 ma v vff linear operation range 0 to 3 v v off ic disable voltage 3 3.15 3.3 v v vfflatch latch off/clamp level v zcd > v zcdth 6.4 v kc control voltage gain (4) v vff = 1 v, v comp = 4 v 0.4 v/v k ff feedforward gain (3) v vff = 1 v, v comp = 4 v 0.04 v/v current sense comparator i cs input bias current v cs = 0 -1 a t leb leading edge blanking 150 250 300 ns td (h-l) delay to output 100 ns v csx overcurrent setpoint v comp = v comphi , v vff = 0 v 0.92 1 1.08 v v comp = v comphi , v vff = 1.5 v 0.45 0.5 0.55 v comp = v comphi , v vff = 3.0 v 0 0.1 v csdis hiccup-mode ocp level (1) 1.4 1.5 1.6 v pwm control v comphi upper clamp voltage i comp = 0 5.7 v table 4. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit electrical characteristics l6566bh 14/51 doc id 16610 rev 2 v complo lower clamp voltage i source = -1 ma 2.0 v v compsh linear dynamics upper limit (1) v vff = 0 v 4.855.2v i comp max. source current v comp = 3.3 v 320 400 480 a r comp dynamic resistance v comp = 2.6 to 4.8 v 25 k ? v compbm burst-mode threshold (1) 2.52 2.65 2.78 v (1) mode/sc = open 2.7 2.85 3 hys burst-mode hysteresis 20 mv i clampl lower clamp capability v comp = 2 v -3.5 -1.5 ma v compoff disable threshold voltage falling 1.4 v v compo level for lower uvlo off threshold (voltage falling) (4) 2.61 2.75 2.89 v (4) mode/sc = open 3.02 3.15 3.28 v compl level for higher uvlo off threshold (voltage rising) (4) 2.93.053.2 v (4) mode/sc = open 3.41 3.55 3.69 zero-current detector/overvoltage protection v zcdh upper clamp voltage i zcd = 3 ma 5.4 5.7 6 v v zcdl lower clamp voltage i zcd = - 3 ma -0.4 v v zcda arming voltage (1) positive-going edge 85 100 115 mv v zcdt triggering voltage (1) negative-going edge 30 50 70 mv i zcd internal pull-up v comp < v compsh -1 a v zcd < 2 v, v comp = v comphi -130 -100 -70 i zcdsrc source current capability v zcd = v zcdl -3 ma i zcdsnk sink current capability v zcd = v zcdh 3ma t blank1 turn-on inhibit time after gate-drive going low 2.5 s v zcdth ovp threshold 4.85 5 5.15 v t blank2 ovp strobe delay after gate-drive going low 2 s latched shutdown function i otp input bias current v dis = 0 to v otp -1 a v otp disable threshold (1) 4.32 4.5 4.68 v thermal shutdown vth shutdown threshold 160 c hys hysteresis 50 c external oscillator (frequency modulation) f fmod oscillation frequency c mod = 0.1 f 600 750 900 hz --- usable frequency range 0.05 15 khz table 4. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit l6566bh electrical characteristics doc id 16610 rev 2 15/51 v pk peak voltage (4) 1.5 v v vy valley voltage 0.5 v i fmod charge/discharge current 150 a mode selection / slope compensation mode th threshold for qr operation 3 v sc pk ramp peak (mode/sc = open) r s-comp = 3 k ? to gnd, gd pin high, v comp = 5 v 1.7 v sc vy ramp starting value (mode/sc = open) r s-comp = 3 k ? to gnd, gd pin high 0.3 v ramp voltage (mode/sc = open) gd pin low 0 v source capability (mode/sc = open) v s-comp = v s-comppk 0.8 ma soft-start i ss1 charge current t j = 25 c, v ss < 2 v, v comp = 4 v 14 20 26 a i ss2 t j = 25 c, v ss > 2 v, v comp = v comphi 3.556.5 i ssdis discharge current v ss > 2 v 3.556.5a v ssclamp high saturation voltage v comp = 4 v 2 v v ssdis disable level (1) v comp = v comphi 4.8555.15v v sslat latch off level v comp = v comphi 6.4 v gate driver v gdh output high voltage i gdsource = 5 ma, vcc = 12 v 9.8 11 v v gdl output low voltage i gdsink = 100 ma 0.75 v i sourcepk output source peak current -0.6 a i sinkpk output sink peak current 0.8 a t f fall time 40 ns t r rise time 50 ns v gdclamp output clamp voltage i gdsource = 5 ma; vcc = 20 v 10 11.3 15 v uvlo saturation vcc = 0 to v ccon , i sink = 1 ma 0.9 1.1 v 1. parameters tracking one another. 2. see table 6 on page 18 and table 7 on page 44 . 3. for the thermal behavior, refer to figure 8 . 4. the voltage feedforward block output is given by: table 4. electrical characteristics (continued) symbol parameter test condition min. typ. max. unit application information l6566bh 16/51 doc id 16610 rev 2 5 application information the l6566bh is a versatile peak-current-mode pwm controller specific to offline flyback converters. the device allows either fixed-frequency (ff) or quasi-resonant (qr) operation, selectable with the mode/sc pin (12): forcing the voltage on the pin over 3 v (e.g. by tying it to the 5 v reference externally available at the vref pin, 10) activates qr operation, otherwise the device is ff-operated. irrespective of the operating option selected by pin 12, the device is able to work in different modes, depending on the converter?s load conditions. if qr operation is selected (see figure 4 ): 1. qr mode at heavy load. quasi-resonant operation lies in synchronizing mosfet turn- on to the transformer?s demagnetization by detecting the resulting negative-going edge of the voltage across any winding of the transformer. then, the system works close to the boundary between discontinuous (dcm) and continuous conduction (ccm) of the transformer. as a result, the switching frequency is different for different line/load conditions (see the hyperbolic-like portion of the curves in figure 4 ). minimum turn-on losses, low emi emission and safe behavior in short-circuit are the main benefits of this kind of operation. 2. valley-skipping mode at medium/ light load. the externally programmable oscillator of the l6566bh, synchronized to mosfet turn-on, enables the user to define the maximum operating frequency of the converter. as the load is reduced, mosfet turn- on no longer occurs on the first valley but on the second one, the third one and so on. in this way the switching frequency no longer increases (piecewise linear portion in figure 4 ). 3. burst-mode with no or very light load. when the load is extremely light or disconnected, the converter enters a controlled on/off operation with constant peak current. decreasing the load then results in frequency reduction, which can go down even to few hundred hertz, therefore minimizing all frequency-related losses and making it easier to comply with energy saving regulations or recommendations. with the peak current very low, no issue of audible noise arises. figure 4. multimode operation with qr option active am114 8 0v1 0 0 f s w pinm a x inp u t volt a ge p in f o s c b u r s t-m ode v a lley- s kipping mode q uas i-re s on a nt mode l6566bh application information doc id 16610 rev 2 17/51 if ff operation is selected: 1. ff mode from heavy to light load. the system operates exactly like a standard current mode control, at a frequency f sw determined by the externally programmable oscillator: both dcm and ccm transformer operations are possible, depending on whether the power that it processes is greater or less than: equation 1 where vin is the input voltage to the converter, v r the reflected voltage (i.e. the regulated output voltage times the primary-to-secondary turn ratio) and lp the inductance of the primary winding. pin t is the power level that marks the transition from continuous to discontinuous operation mode of the transformer. 2. burst-mode with no or very light load. this kind of operation is activated in the same way and results in the same behavior as previously described for qr operation. the l6566bh is specifically designed for applications with no pfc front-end; pin 6 (f mod ) features an auxiliary oscillator that can modulate the switching frequency (when ff operation is selected) in order to mitigate emi emissions by a spread-spectrum action. 5.1 high voltage startup generator figure 5 shows the internal schematic of the high voltage startup generator (hv generator). it is made up of a high voltage n-channel fet, whose gate is biased by a 15 m ? resistor, with a temperature-compensated current generator connected to its source. figure 5. high voltage startup generator: internal schematic with reference to the timing diagram of figure 6 , when power is first applied to the converter the voltage on the bulk capacitor (vin) builds up and, at about 80 v, the hv generator is enabled to operate (hv_en is pulled high) so that it draws about 1 ma. this current, minus the device consumption, charges the bypass capacitor connected from the vcc pin (5) to ground and makes its voltage rise almost linearly. am114 8 1v1 l6566bh 15 mw gnd hv vcc 5 3 1 i ch a rge vcc_ok i hv control hv_en application information l6566bh 18/51 doc id 16610 rev 2 figure 6. timing diagram: normal power-up and power-down sequences as the vcc voltage reaches the turn-on threshold (14 v typ.) the device starts operating and the hv generator is cut off by the vcc_ok signal asserted high. the device is powered by the energy stored in the vcc capacitor until the self-supply circuit (typically an auxiliary winding of the transformer and a steering diode) develops a voltage high enough to sustain the operation. the residual consumption of this circuit is just the one on the 15 m ? resistor ( 10 mw at 400 vdc), typically 50-70 times lower, under the same conditions, as compared to a standard startup circuit made with external dropping resistors. at converter power-down the system loses regulation as soon as the input voltage is so low that either peak current or maximum duty cycle limitation is tripped. vcc then drops and stops ic activity as it falls below the uvlo threshold (10 v typ.). the v cc _ok signal is de- asserted as the vcc voltage goes below a threshold v ccrest located at about 5 v. the hv generator can now restart. however, if vin < vin start , as illustrated in figure 6 , hv_en is de- asserted too and the hv generator is disabled. this prevents converter restart attempts and ensures monotonic output voltage decay at power-down in systems where brownout protection (see the relevant section) is not used. the low restart threshold v ccrest ensures that, during short-circuits, the restart attempts of the device have a very low repetition rate, as shown in the timing diagram of figure 7 , and that the converter works safely with extremely low power throughput. am114 8 2v1 vcc (pin 5) gd (pin 4) hv_en vcc on vcc off vcc re s t a rt t t t t vin v hv s t a rt i ch a rge 0. 8 5 ma t t cc_ok power-on power-off norm a l oper a tion reg u l a tion i s lo s t here l6566bh application information doc id 16610 rev 2 19/51 figure 7. timing diagram showing short-circ uit behavior (ss pin clamped at 5 v) figure 8. v hv rating vs. temperature 5.2 zero-current detection and triggering block; oscillator block the zero-current detection (zcd) and triggering blocks switch on the external mosfet if a negative-going edge falling below 50 mv is applied to the input (pin 11, zcd). to do so, the triggering block must be previously armed by a positive-going edge exceeding 100 mv. this feature is typically used to detect transformer demagnetization for qr operation, where the signal for the zcd input is obtained from the transformer?s auxiliary winding used also to supply the l6566bh. the triggering block is blanked for t blank = 2.5 s after mosfet am114 83 v1 vcc (pin 5) gd (pin 4) vcc_ok vc c on vcc off vc c re s t a rt i ch a rge 0. 8 5 ma s hort circ u it occ u r s here t t t t rep < 0.0 3 t rep am114 8 4v1 0.900 0.920 0.940 0.960 0.9 8 0 1.000 1.020 1.040 1.060 1.0 8 0 -50 -25 0 25 50 75 100 125 150 vhv (norm a lized @ 25 c) tj ( c) application information l6566bh 20/51 doc id 16610 rev 2 turn-off to prevent any negative-going edge that follows leakage inductance demagnetization from triggering the zcd circuit erroneously. the voltage at the pin is both top and bottom limited by a double clamp, as illustrated in the internal diagram of the zcd block of figure 8 . the upper clamp is typically located at 5.7 v, while the lower clamp is located at -0.4 v. the interface between the pin and the auxiliary winding is a resistor divider. its resistance ratio is properly chosen (see section 5.11: ovp block ) and the individual resistance values (r z1 , r z2 ) are such that the current sourced and sunk by the pin is within the rated capability of the internal clamps ( 3 ma). at converter power-up, when no signal is coming from the zcd pin, the oscillator starts up the system. the oscillator is programmed externally by means of a resistor (r t ) connected from the osc pin (13) to ground. with good approximation the oscillation frequency f osc is: equation 2 (with f osc in khz and r t in k ? ). as the device is turned on, the oscillator starts immediately; at the end of the first oscillator cycle, the voltage on the zcd pin being zero, the mosfet is turned on, therefore starting the first switching cycle right at the beginning of the second oscillator cycle. at any switching cycle, the mosfet is turned off as the voltage on the current sense pin (cs, 7) hits an internal reference set by the line feedforward block, and the transformer starts demagnetization. if this completes (so a negative-going edge appears on the zcd pin) after a time exceeding one oscillation period t osc = 1/f osc from the previous turn-on, the mosfet is turned on again ? with some delay to ensure minimum voltage at turn-on ? and the oscillator ramp is reset. if, on the other hand, the negative-going edge appears before t osc has elapsed, it is ignored and only the first negative-going edge after t osc turns on the mosfet and synchronizes the oscillator. in this way one or more drain ringing cycles are skipped (?valley-skipping mode?, figure 9 ) and the switching frequency is prevented from exceeding f osc . note: when the system operates in valley skipping-mode, uneven switching cycles may be observed under some line/load conditions, due to the fact that the off-time of the mosfet is allowed to change with discrete steps of one ringing cycle, while the off-time needed for cycle-by-cycle energy balance may fall in between. therefore, one or more longer switching cycles is compensated by one or more shorter cycles and vice versa. however, this mechanism is absolutely normal and there is no appreciable effect on the performance of the converter or on its output voltage. t 3 osc r 10 2 f ? figure 9. drain ringing cycle skipping as the load is gradually reduced p in = p in' (limit condition) p in = p in'' < p in' p in = p in''' < p in'' t v d s t fw t o s c t v t on t v d s t o s c t v d s t o s c am114 8 5v1 l6566bh application information doc id 16610 rev 2 21/51 if the mosfet is enabled to turn on but the amplitude of the signal on the zcd pin is smaller than the arming threshold for some reason (e.g. a heavy damping of drain oscillations, like in some single-stage pfc topologies, or when a turn-off snubber is used), mosfet turn-on cannot be triggered. this is identical to what happens at startup: at the end of the next oscillator cycle the mosfet is turned on, and a new switching cycle takes place after skipping no more than one oscillator cycle. the operation described so far does not consider the blanking time t blank after mosfet turn-off, and actually t blank does not come into play as long as the following condition is met: equation 3 where d is the mosfet duty cycle. if this condition is not met, there are no substantial changes: the time during which mosfet turn-on is inhibited is extended beyond t osc by a fraction of t blank . as a consequence, the maximum switching frequency is a little lower than the programmed value f osc and valley-skipping mode may take place slightly earlier than expected. however this is quite unusual: setting f osc = 150 khz, the phenomenon can be observed at duty cycles higher than 60%. see section 5.11: ovp block for further implications of t blank . if the voltage on the comp pin (9) saturates high, which reveals an open control loop, an internal pull-up keeps the zcd pin close to 2 v during mosfet off-time to prevent noise from false triggering the detection block. when this pull-up is active, the zcd pin may not be able to go below the triggering threshold, which would stop the converter. to allow auto- restart operation, however ensuring minimum operating frequency in these conditions, the oscillator frequency that retriggers mosfet turn-on is that of the external oscillator divided by 128. additionally, to prevent malfunction at converter startup, the pull-up is disabled during the initial soft-start (see the relevant section). however, to ensure a correct startup, at the end of the soft-start phase the output voltage of the converter must meet the condition: equation 4 where ns is the turn number of the secondary winding, naux the turn number of the auxiliary winding and i zcd the maximum pull-up current (130 a). the operation described so far under different operating conditions for the converter is illustrated in the timing diagrams of figure 10 . if the ff option is selected the operation is exactly equal to that of a standard current-mode pwm controller. it works at a frequency fsw = fosc; both dcm and ccm transformer operations are possible, depending on the operating conditions (input voltage and output load) and on the design of the power stage. the mosfet is turned on at the beginning of each oscillator cycle and is turned off as the voltage on the current sense pin reaches an internal reference set by the line feedforward block. the maximum duty cycle is limited to 70% minimum. the signal on the zcd pin in this case is used only for detecting feedback loop failures (see section 5.11: ovp block ). osc blank t t 1 d ? zcd 1 z i r naux ns vout > application information l6566bh 22/51 doc id 16610 rev 2 5.3 burst-mode operation at no load or very light load when the voltage at the comp pin (9) falls 20 mv below a threshold fixed internally at a value, v compbm , depending on the selected operating mode, the l6566bh is disabled with the mosfet kept in off-state and its consumption reduced to a lower value to minimize v cc capacitor discharge. the control voltage now increases as a result of the feedback reaction to the energy delivery stop (the output voltage is slowly decaying), the threshold is exceeded and the device restarts switching again. in this way the converter works in burst-mode with a nearly constant peak current defined by the internal disable level. a load decrease then causes a frequency reduction, which can go down even to few hundred hertz, therefore minimizing all frequency-related losses and making it easier to comply with energy saving regulations. this kind of operation, shown in the timing diagrams of figure 11 along with the others previously described, is noise-free since the peak current is low. if it is necessary to decrease the intervention threshold of the burst-mode operation, this can be done by adding a small dc offset on the current sense pin as shown in figure 12 . note: the offset reduces the available dynamics of the current signal; thereby, the value of the sense resistor must be determined taking this offset into account. figure 10. operation of zcd, triggering and oscillator blocks (qr option active) am114 8 6v1 a ) f u ll lo a d gd (pin 4) zcd b l a nking time zcd (pin 11) o s cill a tor r a mp pwm l a tch s et pwm l a tch re s et on-en ab le ar m /tr i g g e r 50 mv 100 mv a rmed trigger b ) light lo a d zcd b l a nking time pwm l a tch s et pwm l a tch re s et on-en ab le ar m /tr i g g e r 50 mv 100 mv o s cill a tor r a mp gd (pin 4) zcd (pin 11) c) s t a rt- u p zcd b l a nking time pwm l a tch s et pwm l a tch re s et on-en ab le arm/trigger 50 mv 100 mv o s cill a tor r a mp gd (pin 4) zcd (pin 11) l6566bh application information doc id 16610 rev 2 23/51 figure 11. load-dependent operating modes: timing diagrams figure 12. addition of an offset to the current sense lowers the burst-mode operation threshold 5.4 adaptive uvlo a major problem when optimizing a converter for minimum no-load consumption is that the voltage generated by the auxiliary winding under these conditions falls considerably as compared even to a few ma load. this very often causes the supply voltage vcc of the control ic to drop and go below the uvlo threshold so that the operation becomes intermittent, which is undesired. furthermore, this must be traded off against the need to generate a voltage not exceeding the maximum allowed by the control ic at full load. to help the user overcome this problem, the device, besides reducing its own consumption during burst-mode operation, also features a proprietary adaptive uvlo function. it consists of shifting the uvlo threshold downwards at light load, namely when the voltage at the comp pin falls below a threshold v compo internally fixed, so as to have more headroom. to am114 8 7v1 gd (pin 4) v compbm t t t comp (pin 9) 20 mv hy s ter. qr mode v a lley- s kipping mode b u r s t-m ode f s w f o s c qr mode ff mode b u r s t-m ode ff mode mode/ s c=open mode/ s c=vref mode/ s c=open mode/ s c=vref am114 88 v1 r s l6566bh r vref rc 10 4 7 3 vc s o = vref r r + rc application information l6566bh 24/51 doc id 16610 rev 2 prevent any malfunction during transients from minimum to maximum load the normal (higher) uvlo threshold is re-established when the voltage at the comp pin exceeds v compl and vcc has exceeded the normal uvlo threshold (see figure 13 ). the normal uvlo threshold ensures that at full load the mosfet is driven with a proper gate-to-source voltage. 5.5 pwm control block the device is specific to secondary feedback. typically, there is a tl431 on the secondary side and an optocoupler that transfers output voltage information to the pwm control on the primary side, crossing the isolation barrier. the pwm control input (pin 9, comp) is driven directly by the phototransistor?s collector (the emitter is grounded to gnd) to modulate the duty cycle ( figure 14 , left-hand side circuit). in applications where a tight output regulation is not required, it is possible to use a primary- sensing feedback technique. in this approach the voltage generated by the self-supply winding is sensed and regulated. this solution, shown in figure 14 , right-hand side circuit, is cheaper because no optocoupler or secondary reference is needed, but output voltage regulation, especially as a result of load changes, is quite poor. figure 14. possible feedback configurations that can be used with the l6566bh figure 13. adaptive uvlo block am114 8 9v1 v compl v compo vcomp (pin 9) vcc (pin 5) q vcc off1 vcc off2 t t t (*) vcc off2 < vcc off1 i s s elected when q i s hig h + - uvlo vcc off1 vc c l6566bh comp r s q + - + - vcc off2 (*) s w 5 9 v compl v compo am11490v1 vo u t tl4 3 1 l6566bh 9 comp l6566bh 5 vcc n au x 9 comp c s s econd a ry feed ba ck prim a ry feed ba ck l6566bh application information doc id 16610 rev 2 25/51 ideally, the voltage generated by the self-supply winding and the output voltage should be given by the relation between the naux/ns turn ratio only. actually, numerous non-idealities, mainly transformer parasites, cause the actual ratio to deviate from the ideal one. line regulation is quite good, in the range of 2%, whereas load regulation is about 5% and output voltage tolerance is in the range of 10%. the dynamics of the pin are in the 2.5 to 5 v range. the voltage at the pin is clamped downwards at about 2 v. if the clamp is externally overridden and the voltage on the pin is pulled below 1.4 v, the l6566bh shuts down. this condition is latched as long as the device is supplied. while the device is disabled, however, no energy is coming from the self-supply circuit, therefore the voltage on the vcc capacitor decays and crosses the uvlo threshold after some time, which clears the latch and lets the hv generator restart. this function is intended for an externally controlled burst-mode operation at light load with a reduced output voltage, a technique typically used in multi-output smps, such as those for tvs or monitors (see the timing diagram figure 15 ). figure 15. externally controlled burst-mode operation by driving the comp pin: timing diagram 5.6 pwm comparator, pwm latch and voltage feedforward blocks the pwm comparator senses the voltage across the current sense resistor rs and, by comparing it to the programming signal delivered by the feedforward block, determines the exact time when the external mosfet is to be switched off. its output resets the pwm latch, previously set by the oscillator or the zcd triggering block, which asserts the gate driver output low. the use of pwm latch avoids spurious switching of the mosfet that may result from the noise generated (?double-pulse suppression?). am11491v1 vcc (pin 5) gd (pin 4) vcc_ok vcc on vcc off vcc re s t a rt i ch a rge 0. 8 5 ma s t a nd b y i s comm a nded here t t t t t comp (pin 9) t vo u t application information l6566bh 26/51 doc id 16610 rev 2 cycle-by-cycle current limitation is realized with a second comparator (ocp comparator) that senses the voltage across the current sense resistor rs as well and compares this voltage to a reference value v csx . its output is or-ed with that of the pwm comparator (see the circuit schematic in figure 17 ). in this way, if the programming signal delivered by the feedforward block and sent to the pwm comparator exceeds v csx , it is the ocp comparator to reset first the pwm latch instead of the pwm comparator. the value of v csx , thereby, determines the overcurrent setpoint along with the sense resistor rs. the power that qr flyback converters with a fixed overcurrent setpoint (like fixed-frequency systems) are able to deliver changes considerably with the input voltage. with wide-range mains, at maximum line it can be more than twice the value at minimum line, as shown by the upper curve in the diagram of figure 16 . the device has the line feedforward function available to solve this issue. it acts on the overcurrent setpoint v csx , so that it is a function of the converter?s input voltage vin sensed through a dedicated pin (15, vff): the higher the input voltage, the lower the setpoint. this is illustrated in the diagram on the left-hand side of figure 17 : it shows the relationship between the voltage on the pin vff and v csx (with the error amplifier saturated high in the attempt to obtain output voltage regulation): equation 5 figure 16. typical power capability chan ge vs. input voltage in qr flyback converters note: if the voltage on the pin exceeds 3 v, switching ceases but the soft-start capacitor is not discharged. the schematic in figure 17 shows also how the function is included in the control loop. with a proper selection of the external divider r1-r2, i.e. of the ratio k = r2 / (r1+r2), it is possible to achieve the optimum compensation described by the lower curve in the diagram of figure 16 . the optimum value of k, k opt , which minimizes the power capability variation over the input voltage range, is the one that provides equal power capability at the extremes of the range. the exact calculation is complex, and non-idealities shift the real-world optimum value from vin 3 k 1 3 v 1 v vff csx ? = ? = am11492v1 11.522.5 33 .5 4 0.5 1 1.5 2 2.5 s y s tem optim a lly compen sa ted s y s tem not compen sa ted k = 0 k = k opt k l6566bh application information doc id 16610 rev 2 27/51 the theoretical one. it is therefore more practical to provide a first cut value, simple to calculate, and then to fine tune experimentally. assuming that the system operates exactly at the boundary between dcm and ccm, and neglecting propagation delays, the following expression for k opt can be found: equation 6 experience shows that this value is typically lower than the real one. once the maximum peak primary current, i pkpmax , occurring at minimum input voltage vin min has been found, the value of rs can be determined from (5): equation 7 the converter is then tested on the bench to find the output power level pout lim where regulation is lost (because overcurrent is being tripped) both at vin = vin min and vin = vin max . if pout lim @ vin max > pout lim @ vin min the system is still undercompensated and k needs to increase; if pout lim @ vin max < pout lim @ vin min the system is overcompensated and k needs to decrease. this goes on until the difference between the two values is acceptably low. once the true k opt is found in this way, it is possible that pout lim can turn out slightly different from the target; to correct this, the sense resistor rs needs to be adjusted and the above tuning process is repeated with the new rs value. typically, a satisfactory setting is achieved in no more than a couple of iterations. () r max in min in max in min in r opt v v v v v v 3 k ? + + ? ? = max pkp min in opt i v 3 k 1 rs ? = figure 17. left: overcurrent setpoint vs. vff voltage; right: line feedforward function block am1149 3 v1 v c s x [v] 0 0.5 1 1.5 2 2.5 33 .5 0 0.2 0.4 0.6 0. 8 1 1.2 v vff [v] v comp = upper cl a mp 7 9 15 r s rectified line volt a ge driver 4 r s q r1 r2 comp vff c s gd l6566bh 1.5 v + - hicc u p di s able voltage feed forward option a l for ovp s etting s ocp + - pwm + - vc s x clock/zcd application information l6566bh 28/51 doc id 16610 rev 2 in applications where this function is not wanted, e.g. because of a narrow input voltage range, the vff pin can be simply grounded, directly or through a resistor, depending on whether the user wants the ovp function to be auto-restart or latched mode (see ? section 5.11: ovp block ?). the overcurrent setpoint is then fixed at the maximum value of 1 v. if a lower setpoint is desired to reduce the power dissipation on rs, the pin can be also biased at a fixed voltage using a divider from vref (pin 10). if the ff option is selected the line feedforward function can be still used to compensate for the total propagation delay td of the current sense chain (internal propagation delay td (h-l) plus the turn-off delay of the external mosfet), which in standard current mode pwm controllers is done by adding an offset on the current sense pin proportional to the input voltage. in that case the divider ratio k, which is much smaller as compared to that used with the qr option selected, can be calculated with the following equation: equation 8 where lp is the inductance of the primary winding. in case a constant maximum power capability vs. the input voltage is not required, the vff pin can be grounded, directly or through a resistor (see section 5.11: ovp block ), therefore fixing the overcurrent setpoint at 1 v, or biased at a fixed voltage through a divider from vref to obtain a lower setpoint. it is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nf) to ensure a clean operation of the ic even in a noisy environment. the pin is internally forced to ground during uvlo, after activating any latched protection and when the comp pin is pulled below its low clamp voltage (see section 5.5: pwm control block ). 5.7 hiccup-mode ocp a third comparator senses the voltage on the current sense input and shuts down the device if the voltage on the pin exceeds 1.5 v, a level well above that of the maximum overcurrent setpoint (1 v). such an anomalous condition is typically generated by either a short-circuit of the secondary rectifier or a shorted secondary winding or a hard-saturated flyback transformer. lp rs td 3 k opt = l6566bh application information doc id 16610 rev 2 29/51 figure 18. hiccup-mode ocp: timing diagram to distinguish an actual malfunction from a disturbance (e.g. induced during esd tests), the first time the comparator is tripped the protection circuit enters a ?warning state?. if in the next switching cycle the comparator is not tripped, a temporary disturbance is assumed and the protection logic is reset in its idle state; if the comparator is again tripped, a real malfunction is assumed and the l6566bh is stopped. depending on the time relationship between the detected event and the oscillator, the device may occasionally stop after the third detection. this condition is latched as long as the device is supplied. while it is disabled, however, no energy comes from the self-supply circuit; hence the voltage on the v cc capacitor decays and crosses the uvlo threshold after some time, which clears the latch. the internal startup generator is still off, and the v cc voltage still needs to go below its restart voltage before the v cc capacitor is charged again and the device restarted. ultimately, this results in a low-frequency intermittent operation (hiccup-mode operation), with very low stress on the power circuit. this special condition is illustrated in the timing diagram of figure 18 . 5.8 frequency modulation to alleviate the converter?s emi emissions and reduce cost and size of the line filter, it is advantageous to modulate its switching frequency, so that the resulting spread-spectrum action distributes the energy of each harmonic of the switching frequency over a number of side-band harmonics. their overall energy is unchanged but the individual amplitudes are smaller. this is what naturally occurs with qr operation, due to the twice-mains-frequency ripple appearing on the input bulk capacitor, which translates into different dcm-ccm boundary frequencies. the l6566bh is provided with a dedicated pin, f mod (6), to perform this function if ff mode is selected. am11494v1 vcc (pin 5) gd (pin 4) ocp l a tch vc c on vcc off vc c re s t a rt s econd a ry diode i s s horted here t t t t v c s (pin 7) vcc_ok t 1.5 v application information l6566bh 30/51 doc id 16610 rev 2 figure 19. frequency modulation circuit with reference to figure 19 , the capacitor c mod is connected from f mod to ground and is alternately charged and discharged between 0.5 and 1.5 v by internal current generators sourcing and sinking the same current (three times the current defined by the resistor r t on pin osc). therefore, the voltage across c mod is a symmetric triangle, whose frequency f m is determined by c mod . by connecting a resistor r mod from r mod to osc, the current sourced by the osc pin is modulated according to a triangular profile at a frequency f m . if r mod is considerably higher than r t , as is normal, both f m and the symmetry of the triangle is little affected. with this arrangement it is possible to set, nearly independently, the frequency deviation ? f sw and the modulating frequency f m , which define the modulation index: equation 9 which is the parameter that the amplitude of the generated side-band harmonics depends on. the minimum frequency f sw_min (occurring on the peak of the triangle) and the maximum frequency f sw_max (occurring on the valley of the triangle) is symmetrically placed around the centre value f sw , so that: equation 10 then, r t is found from (5) (see section 5.2: zero-current detection and triggering block; oscillator block ), while r mod and c mod can be calculated as follows: equation 11 am11495v1 l6566bh o s c 6 r t fmod 1 3 r mod c mod 1.5 v 0.5 v 0 v 1 v m sw f f ? = sw 2 1 sw max _ sw sw 2 1 sw min _ sw f f f ; f f f ? + = ? ? = sw 3 mod f 10 2 r ? ? = m mod f 75 c = l6566bh application information doc id 16610 rev 2 31/51 where ? f sw and f m (in khz, with c mod in nf and r mod in k ? ) are selected by the user as to achieve the best compromise between attenuation of peak emi emissions and clean converter operation. 5.9 latched disable function the device is equipped with a comparator having the non-inverting input externally available at the pin dis (8) and with the inverting input internally referenced to 4.5 v. as the voltage on the pin exceeds the internal threshold, the device is immediately shut down and its consumption reduced to a low value. the information is latched and it is necessary to let the voltage on the vcc pin go below the uvlo threshold to reset the latch and restart the device. to keep the latch supplied as long as the converter is connected to the input source, the hv generator is activated periodically so that vcc oscillates between the startup threshold v ccon and v ccon - 0.5 v. activating the hv generator in this way cuts its power dissipation approximately by three (as compared to continuous conduction) and keeps peak silicon temperature close to the average value. to let the l6566bh restart, it is then necessary to disconnect the converter from the input source. pulling pin 16 (ac_ok) below the disable threshold (see section 5.12: brownout protection ) stops the hv generator until vcc falls below v ccrestart , so that the latch can be cleared and a quicker restart is allowed as the input source is removed. this operation is shown in the timing diagram of figure 20 . this function is useful in order to implement a latched overtemperature protection very easily by biasing the pin with a divider from vref, where the upper resistor is an ntc physically located close to a heating element like the mosfet, or the transformer. the dis pin is a high impedance input, therefore it is prone to pick-up noise, which may lead to undesired latch off of the device. it is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nf) to prevent any malfunctioning of this kind. application information l6566bh 32/51 doc id 16610 rev 2 figure 20. operation after latched di sable activation: timing diagram 5.10 soft-start and delayed latched shutdown upon overcurrent at device startup, a capacitor (c ss ) connected between the ss pin (14) and ground is charged by an internal current generator, i ss1 , from zero up to about 2 v where it is clamped. during this ramp, the overcurrent setpoint progressively rises from zero to the value imposed by the voltage on the vff pin (15, see section 5.6: pwm comparator, pwm latch and voltage feedforward blocks ); mosfet conduction time increases gradually, therefore controlling the startup inrush current. the time needed for the overcurrent setpoint to reach its steady-state value, referred to as soft-start time, is approximately: equation 12 during the ramp (i.e. until v ss = 2 v) all the functions that monitor the voltage on the comp pin are disabled. the soft-start pin is also invoked whenever the control voltage (comp) saturates high, which reveals an open loop condition for the feedback system. this condition very often occurs at startup, but may be also caused by either a control loop failure or a converter overload/short-circuit. a control loop failure results in an output overvoltage that is handled by the ovp function of the l6566bh (see next section). in the case of qr operation, a short-circuit causes the converter to run at a very low frequency, then with very low power capability. this makes the self-supply system that powers the device unable to keep it operating, so that the converter works intermittently, which is very safe. in the case of am11496v1 vcc (pin 5) gd (pin 4) vin vcc on vcc on -0.5 t t t t 4.5v vcc off di s (pin 8 ) vcc re s t a rt v hv s t a rt hv gener a tor i s t u rned on hv gener a tor t u rn-on i s di sab led here inp u t s o u rce i s removed here t ac_ok (pin 16) vth di sab le l a tch i s re s et here re s t a rt i s qu icker ? ? ? ? ? ? ? ? ? = = 3 v 1 i css ) v ( v i css t vff 1 ss vff csx 1 ss ss l6566bh application information doc id 16610 rev 2 33/51 overload, the system has a power capability lower than that at nominal load but the output current may be quite high and can overstress the output rectifier. in the case of ff operation the capability is almost unchanged and both short-circuit and overload conditions are more critical to handle. the l6566bh, regardless of the operating option selected, makes it easier to handle such conditions: the 2 v clamp on the ss pin is removed and a second internal current generator i ss2 = i ss1 /4 continues to charge c ss . as the voltage reaches 5 v the device is disabled, if it is allowed to reach 2 v be over 5 v, the device is latched off. in the former case the resulting behavior is identical to that of short-circuit illustrated in figure 7 ; in the latter case the result is identical to that of figure 20 . see section 5.9: latched disable function for additional details. a diode, with the anode to the ss pin and the cathode connected to the vref pin (10), is the simplest way to select either auto-restart mode or latch-mode behavior upon overcurrent. if the overload disappears before the css voltage reaches 5 v, the i ss2 generator is turned off and the voltage gradually brought back down to 2 v. refer to section 6: application examples and ideas ( ta bl e 7 ) for additional information. if latch-mode behavior is desired also for converter short-circuit, make sure that the supply voltage of the device does not fall below the uvlo threshold before activating the latch. figure 21 shows soft-start pin behavior under different operating conditions and with different settings (latch-mode or auto-restart). note: unlike other pwm controllers provided with a soft-start pin, in the l6566bh grounding the ss pin does not guarantee that the gate driver is disabled. 5.11 ovp block the ovp function of the l6566bh monitors the voltage on the zcd pin (11) in mosfet off-time, during which the voltage generated by the auxiliary winding tracks the converter?s output voltage. if the voltage on the pin exceeds an internal 5 v reference, a comparator is triggered, an overvoltage condition is assumed and the device is shut down. an internal current generator is activated that sources 1 ma out of the vff pin (15). if the vff voltage figure 21. soft-start pin operation under different operating conditions and settings am11497v 1 t vcc (pin 5) ss ( pin 14) t t comp (pin 9) s tart-up temporary overload overload t gd (pin 4) normal operation normal operation re s tart here the ic s h u t s down here the ic l a tche s off vcc f a ll s b elow uvlo b efore l a tching off s hutdown latched autore s tart uvlo 2v 5v 5v+2v b e application information l6566bh 34/51 doc id 16610 rev 2 is allowed to reach 2 vbe over 5 v, the l6566bh is latched off. see section 5.9: latched disable function for more details on ic behavior under these conditions. if the impedance externally connected to pin 15 is so low that the 5+2 v be threshold cannot be reached or if some means is provided to prevent that, the device is able to restart after the vcc has dropped below 5 v. refer to section 6: application examples and ideas ( ta bl e 7 ) for additional information. figure 22. ovp function: internal block diagram the zcd pin is connected to the auxiliary winding through a resistor divider r z1 , r z2 (see figure 8 ). the divider ratio k ovp = r z2 / (r z1 + r z2 ) is chosen equal to: equation 13 where vout ovp is the output voltage value that is to activate the protection, ns the turn number of the secondary winding, and naux the turn number of the auxiliary winding. am1149 8 v1 f au lt 2- b it co u nter r q1 s mono s t ab le m1 s trobe ov p cout 2 s 0.5 s mono s t ab le m2 - + 5 v zcd co u nter re s et ff 40kw 5pf pwm l a tch q q s r 11 to triggering b lock l6566bh naux ns vout 5 k ovp ovp = l6566bh application information doc id 16610 rev 2 35/51 figure 23. ovp function: timing diagram the value of r z1 is such that the current sourced by the zcd pin be within the rated capability of the internal clamp: equation 14 where vin max is the maximum dc input voltage and ns the turn number of the primary winding. see section 5.2: zero-current detection and triggering block; oscillator block for additional details. to reduce sensitivity to noise and prevent the latch from being erroneously activated, firstly the ovp comparator is active only for a small time frame (typically, 0.5 s) starting 2 s after mosfet turn-off, to reject the voltage spike associated to the positive-going edges of the voltage across the auxiliary winding vaux; secondly, to stop the l6566bh, the ovp comparator must be triggered for four consecutive switching cycles. a counter, which is reset every time the ovp comparator is not triggered in one switching cycle, is provided for this purpose. figure 22 shows the internal block diagram, while the timing diagrams in figure 23 illustrate the operation. note: to use the ovp function effectively, i.e. to ensure that the ovp comparator is always interrogated during mosfet off-time, the duty cycle d under open loop conditions must fulfill the following inequality: am11499v1 t gd (pin 4) vaux 5v t t t strobe t counter reset t counter status t 0 zcd (pin 11) 2 s 0.5 s ovp fault 00 00 11 22 00 11 22 33 4 0 e r u l i a f p o o l k c a b d e e f e c n a b r u t s i d y r a r o p m e t n o i t a r e p o l a m r o n t cout t max 3 1 z vin np naux 10 3 1 r ? ? application information l6566bh 36/51 doc id 16610 rev 2 equation 15 where t blank2 = 2 s; this is also illustrated in the diagram of figure 24 . 5.12 brownout protection brownout protection is basically a not-latched device shutdown function activated when a condition of mains undervoltage is detected. there are several reasons why it may be desirable to shut down a converter during a brownout condition, which occurs when the mains voltage falls below the minimum specification of normal operation. firstly, a brownout condition may cause overheating of the primary power section due to an excess of rms current. secondly, spurious restarts may occur during converter power down, therefore causing the output voltage to not decay to zero monotonically. l6566bh shutdown upon brownout is accomplished by means of an internal comparator, as shown in the block diagram of figure 25 , which shows the basic usage. the inverting input of the comparator, available on the ac_ok pin (16), is supposed to sense a voltage proportional to the rms (peak) mains voltage; the non-inverting input is internally referenced to 0.485 v with 35 mv hysteresis. if the voltage applied on the ac_ok pin before the device starts operating does not exceed 0.485 v or if it falls below 0.45 v while the device is running, the ac_fail signal goes high and the device shuts down, with the soft- start capacitor discharged and the gate-drive output low. additionally, if the device has been latched off by some protection function (testified by vcc oscillating between v ccon and v ccon - 0.5 v) the ac_ok voltage falling below 0.45 v clears the latch. this may allow a quicker restart as the input source is removed. while the brownout protection is active the startup generator keeps on working but, there being no pwm activity, the vcc voltage continuously oscillates between the startup and the hv generator restart thresholds, as shown in the timing diagram of figure 25 . figure 24. maximum allowed duty cycle vs. switching frequency for correct ovp detection 1 f t d sw 2 blank + am11500v 1 5 . 10 4 1 . 10 5 1.5 . 10 5 2 . 10 5 2.5 . 10 5 3 . 10 5 3 .5 . 10 5 4 . 10 5 0.2 0. 3 0.4 0.5 0.6 0.7 0. 8 0.725 f s w [ h z ] dm a x l6566bh application information doc id 16610 rev 2 37/51 figure 25. brownout protection: intern al block diagram and timing diagram the brownout comparator is provided with current hysteresis in addition to voltage hysteresis: an internal 15 a current sink is on as long as the voltage applied on the ac_ok pin is such that the ac_fail signal is high. this approach provides an additional degree of freedom: it is possible to set the on threshold and the off threshold separately by properly choosing the resistors of the external divider (see below). with just voltage hysteresis, on the other hand, fixing one threshold automatically fixes the other one depending on the built-in hysteresis of the comparator. with reference to figure 25 , the following relationships can be established for the on (vsen on ) and off (vsen off ) thresholds of the sensed voltage: equation 16 which, solved for r h and r l , yields: equation 17 am11501v1 s en s ed volt a ge vcc (pin 5) v s en on v s en off gd (pin 4) vo u t vac_ok (pin 16) i hy s 15 a t t t t t t t ac_fail 0.45v 0.4 8 5v - + l6566bh ac_fail ac_ok vcc 16 5 0.4 8 5v 0.45v 15 a r h r l s en s ed volt a ge l h off l 6 h on r 45 . 0 r 45 . 0 vsen r 485 . 0 10 15 r 485 . 0 vsen = ? + ? = ? ? 45 . 0 vsen 45 . 0 r r ; 10 15 vsen 078 . 1 vsen r off h l 6 off on h ? = ? ? ? = ? application information l6566bh 38/51 doc id 16610 rev 2 figure 26. voltage sensing techniques to implement brownout protection with the l6566bh it is usually convenient to use a single divider to bias both the ac_ok and the vff pins, as shown in figure 26 : this is possible because in all practical cases the voltage on the vff pin is lower than that on the ac_ok pin. once r h and r l have been found, as suggested above, and k opt , either calculated from (6) or (8) or experimentally found, r l is split as: equation 18 circuit a) senses the input voltage bus (across the bulk capacitor, downstream of the bridge rectifier); in this case, for a proper operation of the brownout function, vsen on must be lower than the peak voltage at minimum mains and vsen off lower than the minimum voltage on the input bulk capacitor at minimum mains and maximum load considering, if necessary, holdup requirements during mains missing cycles as well. brownout level is load- dependent. in case of latched shutdown, when the input source is removed it is necessary to wait until the bulk capacitor voltage falls below the start voltage of the hv generator v hvstart in order for the unit to restart, which may take up to several seconds. circuit b) senses the mains voltage directly, upstream of the bridge rectifier. it can be configured either for half-wave sensing (only the line/neutral wire is sensed) or full-wave sensing (both neutral and line are sensed); in the first case, assuming c f is large enough, the sensed voltage is equal to 1/ the peak mains voltage, while in the second case it is equal to 2/ the peak mains voltage. c f needs to be quite a big capacitor (in the uf) to have small residual ripple superimposed on the dc level; as a rule-of-thumb, use a time constant r l c f at least 4-5 times the maximum line cycle period in case of half-wave sensing, 2-3 times in case of full-wave sensing. then fine tune if needed, considering also transient conditions such as mains missing cycles. brownout level does not depend on the load. when the input source is removed, c f is discharged after some ten ms then this circuit is suitable for a quick restart after a latched shutdown. the ac_ok pin is a high impedance input connected to high value resistors, therefore it is prone to pick-up noise, which might alter the off threshold when the converter is running or lead to undesired switch-off of the device during esd tests. it is possible to bypass the pin to ground with a small film capacitor (e.g. 1-10 nf) to prevent any malfunctioning of this kind. am11502v1 hv inp u t bus ac_ok 16 r h r l vff 15 option a l for ovp s etting s r l1 r l2 l6566bh a ) b ) ac m a in s (l/n) 16 r h r l 15 ac_ok vff r l1 r l2 l6566bh option a lfor ovp s etting s ac m a in s (n/l) r h c f () 2 l l 1 l h l opt 2 l r r r ; r r k r ? = + = l6566bh application information doc id 16610 rev 2 39/51 the voltage on the pin is clamped upwards at about 3.15 v; then, if the function is not used, the pin must be connected to vcc through a resistor (220 to 680 k ? ). 5.13 slope compensation the mode/sc pin (12), when not connected to vref, provides a voltage ramp during mosfet on-time synchronous to that of the internal oscillator sawtooth, with 0.8 ma minimum current capability. this ramp is intended for implementing additional slope compensation on current sense. this is needed to avoid the sub-harmonic oscillation that arises in all peak-current-mode-controlled converters working at fixed frequency in continuous conduction mode with a duty cycle close to or exceeding 50%. figure 27. slope compensation waveforms the compensation is realized by connecting a programming resistor between this pin and the current sense input (pin 7, cs). the cs pin must be connected to the sense resistor with another resistor to make a summing node on the pin. since no ramp is delivered during mosfet off-time (see figure 27 ), no external component other than the programming resistor is needed to ensure a clean operation at light loads. note: the addition of the slope compensation ramp reduces the available dynamics of the current signal; thereby, the value of the sense resistor must be determined taking this into account. note also that the burst-mode threshold (in terms of power) is slightly changed. if slope compensation is not required with ff operation, the pin is left floating. 5.14 summary of l6566bh power management functions the device is provided with a number of power management functions : multiple operating mode upon loading conditions and protection functions. to help the user familiarize themselves with these functions, in the following tables, all themes are summarized with their respective activation mechanism and the resulting status of the most important pins. this can be useful not only for a correct use of the ic but also for diagnostic purposes: especially at the prototyping/debugging stage, it is quite common to come across unwanted activation of some function, and these tables can be used as a kind of quick troubleshooting guide. am1150 3 v1 intern a l o s cill a tor gd (pin 4) mode/ s c (pin 12) t t t application information l6566bh 40/51 doc id 16610 rev 2 table 5. l6566bh light load management features feature description caused by ic behavior v cc _restart (v) consump. (iqdis,ma) vref (v) ss vcomp (v) osc (v) fmod burst mode controlled on-off operation for low power consumption at light load v comp < v compbm - hys pulse skipping operation n.a. 1.34 ma 5 unchanged v compbm-hys to v compbm 0/1 0 table 6. l6566bh protection protection description caused by ic behavior vcc restart (v) ic iq (ma) vref (v) ss vcomp (v) osc (v) fmod vff ovp output overvoltage protection v zcd >v zcdth for 4 consecutive switching cycles auto restart (1) 52.25 (6) unchanged (6) 0 0 0 unchanged vff > vfflatch latched 13.5 0.33 0 0 0 0 0 0 olp output overload protection v comp =v comphi v ss > v ssdis auto restart (2) 51.465 (6) v ss application information l6566bh 41/51 doc id 16610 rev 2 otp externally settable overtemperature protection v dis >v otp latched 13.5 0.33 0 0 0 0 0 0 internal shutdown t j > 160 o c auto restart (5) 50.330 0 0 0 0 0 brownout mains undervoltage protection v ac_ok < v th auto restart 5 0.33 0 0 0 0 0 unchanged reference drift v ref drift protection v ref > v ov latched 13.5 0.33 0 0 0 0 0 0 shutdown1 gate driver disable v ff > v off auto restart 5 2.5 5 unchanged unchanged 1 unchanged unchanged shutdown2 shutdown by v comp low v comp < v compoff latched 10 0.33 0 0 0 0 0 0 adaptive uvlo shutdown by v cc going below v ccoff (lowering of v ccoff threshold at light load) v cc < 9.4 v ( vcomp > v compl ) auto restart 5 v 0.18m a 00 000 0 v cc < 7.2 v ( vcomp > v compo ) 1. use one external diode from v ff (#15) to ac_ok (#16), cathode to ac_ok. 2. use one external diode from ss (#14) to v ref (#10), cathode to v ref . 3. if c ss and the v cc capacitor are such that v cc falls below uvlo before latch tripping ( figure 21 ). 4. if c ss and the vcc capacitor are such that the latch is tripped before v cc falls below uvlo ( figure 21 ). 5. when t j < 110 o c. 6. discharged to zero by v cc going below uvlo. table 6. l6566bh protection (continued) protection description caused by ic behavior vcc restart (v) ic iq (ma) vref (v) ss vcomp (v) osc (v) fmod vff application information l6566bh 42/51 doc id 16610 rev 2 it is worth remembering that ?auto-restart? means that the device works intermittently as long as the condition that is activating the function is not removed; ?latched? means that the device is stopped as long as the unit is connected to the input power source and the unit must be disconnected for some time from the source in order for the device (and the unit) to restart. optionally, a restart can be forced by pulling the voltage of pin 16 (ac_ok) below 0.45 v. l6566bh application examples and ideas doc id 16610 rev 2 43/51 6 application examples and ideas figure 28. typical low-cost application schematic ) # , " ( # # 1 2 $ 2 # $ # 9 2 2 # ! " 4 : # $ ' $ # 3 6 c c ! # ? / + ' . $ 6 & & # / - 0 $ ) # 2 $ # 2 # 3 3 # 6 2 % & - / $ % 3 # # 2 ( 6 3 & - / $ / 3 # $ ) 3 4 , 2 2 k 2 6 o u t / p t i o n a l f o r 1 2 o p e r a t i o n / p t i o n a l f o r 1 2 o p e r a t i o n 6 i n p h a s e r e c t i f i e r % - ) f i l t e r ! - v figure 29. typical full-feature application schematic (qr operation) ! - v ) # , " ( 6 o u t # 2 # 1 2 $ . 2 $ # 9 # ! " 4 : # $ ' $ # 3 6 c c $ ) 3 ' . $ 6 & & # / - 0 $ ) # 0 # ! 2 $ . # 2 # 3 3 # 6 2 % & & - / $ # 2 ( 6 3 / 3 # ! # ? / + 2 - / $ % 3 # 2 2 2 2 2 # 2 2 4 , 2 . 4 # p h a s e r e c t i f i e r % - ) f i l t e r 6 i n application examples and ideas l6566bh 44/51 doc id 16610 rev 2 figure 30. typical full-feature application schematic (ff operation) ! - v ) # , " ( 6 o u t # 2 # 1 2 $ . 2 $ # 9 # ! " 4 : # $ ' $ # 3 6 c c $ ) 3 ' . $ 6 & & # / - 0 $ ) # 0 # ! 2 $ . # 2 # 3 3 # 6 2 % & - / $ % 3 # # 2 ( 6 3 / 3 # ! # ? / + 2 & - / $ # 2 2 2 2 2 2 2 2 # 2 2 4 , 2 . 4 # p h a s e r e c t i f i e r % - ) f i l t e r 6 i n table 7. external circuits that determine ic behavior upon ovp and ocp ovp latched ovp auto-restart ocp latched ocp auto-restart l6566bh application examples and ideas doc id 16610 rev 2 45/51 figure 31. frequency foldback at light load (ff operation) figure 32. latched shutdown upon mains overvoltage am11504v1 r1 l6566bh vref r t 10 9 1 3 comp o s c bc 8 57c mode/ s c 12 r2 am11504v1 l6566bh vcc 5 8 vff bc 8 47 di s vin 15 l6566bh 8 vff bc 8 57 di s vin 15 vref 10 r q >10 r q package mechanical data l6566bh 46/51 doc id 16610 rev 2 7 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com . ecopack is an st trademark. table 8. SO16N mechanical data dim. mm min. typ. max. a 1.75 a1 0.10 0.25 a2 1.25 b0.31 0.51 c0.17 0.25 d 9.80 9.90 10.00 e5.806.006.20 e1 3.80 3.90 4.00 e1.27 h0.25 0.50 l0.40 1.27 k0 8 ccc 0.10 l6566bh package mechanical data doc id 16610 rev 2 47/51 figure 33. SO16N package drawing 0016020_f package mechanical data l6566bh 48/51 doc id 16610 rev 2 figure 34. recommended footprint (dimensions are in mm) l6566bh order codes doc id 16610 rev 2 49/51 8 order codes table 9. order codes order codes package packaging l6566bh SO16N tube l6566bhtr SO16N tape and reel revision history l6566bh 50/51 doc id 16610 rev 2 9 revision history table 10. document revision history date revision changes 30-nov-2009 1 first release 16-apr-2012 2 updated internal voltage reference: typical value from 800 v to 840 v in the entire document. updated: ta bl e 2 and table 4 . added footnote 4 on ta b l e 4 . updated figure 8 . and section 7: package mechanical data . minor text changes. l6566bh doc id 16610 rev 2 51/51 please read carefully: information in this document is provided solely in connection with st products. stmicroelectronics nv and its subsidiaries (?st ?) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described he rein at any time, without notice. all st products are sold pursuant to st?s terms and conditions of sale. purchasers are solely responsible for the choice, selection and use of the st products and services described herein, and st as sumes no liability whatsoever relating to the choice, selection or use of the st products and services described herein. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. i f any part of this document refers to any third party products or services it shall not be deemed a license grant by st for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoev er of such third party products or services or any intellectual property contained therein. unless otherwise set forth in st?s terms and conditions of sale st disclaims any express or implied warranty with respect to the use and/or sale of st products including without limitation implied warranties of merchantability, fitness for a particular purpose (and their equivalents under the laws of any jurisdiction), or infringement of any patent, copyright or other intellectual property right. unless expressly approved in writing by two authorized st representatives, st products are not recommended, authorized or warranted for use in military, air craft, space, life saving, or life sustaining applications, nor in products or systems where failure or malfunction may result in personal injury, death, or severe property or environmental damage. st products which are not specified as "automotive grade" may only be used in automotive applications at user?s own risk. resale of st products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by st for the st product or service described herein and shall not create or extend in any manner whatsoev er, any liability of st. st and the st logo are trademarks or register ed trademarks of st in various countries. information in this document supersedes and replaces all information previously supplied. the st logo is a registered trademark of stmicroelectronics. all other names are the property of their respective owners. ? 2012 stmicroelectronics - all rights reserved stmicroelectronics group of companies australia - belgium - brazil - canada - china - czech republic - finland - france - germany - hong kong - india - israel - ital y - japan - malaysia - malta - morocco - philippines - singapore - spain - sweden - switzerland - united kingdom - united states of america www.st.com |
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